Professor Messer A+ 220-1201 objective 3.3 — RAM vs storage, DIMM and SO-DIMM, 64-bit data width, SDRAM, double data rate, and DDR3/DDR4/DDR5 compatibility and keying.
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Professor Messer A+ 220-1201 objective 3.3 — parity memory and even-parity calculation, ECC memory, memory bandwidth in MT/s, and multi-channel RAM.
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Full class notes for Professor Messer A+ 220-1201 objective 3.3: RAM vs storage, DIMM and SO-DIMM, 64-bit data width, SDRAM, double data rate, and DDR3/DDR4/DDR5 compatibility and keying.
Lesson Note
Full class notes for Professor Messer A+ 220-1201 objective 3.3: parity memory and even-parity calculation, ECC memory, memory bandwidth in MT/s, and multi-channel RAM.
Lesson Note
Code ch. 17 — feeding outputs back to inputs: the oscillator (a clock), R-S flip-flops, D latches, edge-triggered flip-flops, dividers and counters.
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Code ch. 19 — building RAM from latches: addresses, decoders to write, selectors to read, address lines vs capacity, and why RAM is volatile.
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